1. Field of the Invention
The present invention is generally in the field of circuit design. More specifically, the present invention is in the field of designing circuits including at least one inductor.
2. Background Art
The demand for advanced consumer electronic devices, such as cellular phones, information assistants, and personal computers, has challenged semiconductor manufacturers to reduce the time-to-market for the integrated circuits (xe2x80x9cICxe2x80x9d) these products contain. In an effort to meet that challenge, semiconductor manufacturers use automated design systems that provide the designer with sets of tools and methodologies that reduce the entire design cycle of the IC.
A typical IC design system includes a design cycle that comprises various steps. For example, the steps in an IC design cycle can include circuit design and simulation, circuit layout generation, circuit layout verification, and extraction of parasitics from the circuit layout. The initial circuit design and simulation is performed before the designer has knowledge of the exact layout of the entire circuit, which is generated later in the design cycle. As a result, the designer has to attempt to predict and counteract the effect of various parasitics that might be introduced during layout design, which can severely degrade circuit performance.
Timing, voltage levels, and race conditions have to be re-verified after the designer knows of exact parasitics, such as parasitic capacitance, resistance, and inductance, extracted from circuit layout. Thus, a new circuit simulation incorporating correct values of the extracted parasitics from the circuit layout is required. Even then, the new circuit layout will often result in different values of extracted parasitics. Some parasitics may be eliminated, some new ones may be introduced, and some may increase or decrease, as such resulting in the need to redesign and re-simulate the circuit. The above steps are repeated, where the circuit design is modified by re-extracted parasitics from the circuit layout.
Without precise knowledge of the effect circuit modifications have on parasitics extracted from the circuit layout, the designer has to continually attempt to predict what new parasitics might be generated from the latest circuit modifications. Thus, the circuit""s design cycle continues through numerous, time consuming iterations until the circuit layout parasitics have been correctly taken into account during the circuit design and simulation cycle. This repetitious cycle can result in many days or weeks of delay in completion of the circuit design for large circuit blocks. The resulting increase in xe2x80x9ctime-to-marketxe2x80x9d causes a tremendous economic loss to semiconductor design houses and manufacturers.
FIG. 1 shows flowchart 100, which illustrates a typical sequence of steps in a circuit""s design, layout, and verification. In step 102 in FIG. 1, a circuit is designed and a schematic for the circuit is made. The circuit is also simulated in step 102. The circuit can be designed with the assistance of a commercial circuit design editor, such as Composer(copyright), by Cadence Design Systems(copyright), Inc. A simulation program can simulate the electrical behavior of a circuit using the parameters that were input for the circuit""s components. The circuit simulation can be written and performed, for example, by using the SPECTRE(copyright) program. However, the accuracy of the results obtained from the circuit simulation depend on the accuracy of all the circuit components, including a large number of parasitic components in the actual layout of the circuit, whose values cannot generally be accurately estimated by conventional design techniques.
In step 104, a circuit layout is generated using a layout generator. The layout generator program can be written in SKILL(copyright), C++, a combination of the two languages, or a combination of a number of other languages. In step 106 in FIG. 1, a design rule check (xe2x80x9cDRCxe2x80x9d) and a layout versus circuit schematic (xe2x80x9cLVSxe2x80x9d) verification is performed on the circuit layout generated in step 104. DRC is performed to ensure that the circuit layout conforms to all manufacturing specifications. For example, the DRC program identifies problems such as xe2x80x9cminimum-spacingxe2x80x9d violations and xe2x80x9cminimum-widthxe2x80x9d violations. In LVS, the circuit layout is checked against the circuit schematic to ensure electrical equivalence. In other words, the circuit layout is checked to see that it corresponds to the circuit schematic. By way of example, the LVS checking can be implemented using the Calibre(copyright) program and a rule file written in Calibrexc2x0 format.
In step 108, parasitics are extracted from the circuit layout. For example, in an inductor""s layout, both the inductor""s xe2x80x9cinternalxe2x80x9d parasitics and the parasitics generated by the interconnect routing between the inductor and other circuit components are extracted. The inductor""s internal parasitics can include, among other things, the capacitance between the inductor metal segments and the substrate, and the series resistance of the inductor.
It is noted that the inductor""s internal parasitics have a great effect on circuit performance. The internal and interconnect routing parasitics are used by the circuit designer to modify the circuit schematic in step 102, and the circuit design cycle comprising steps 102, 104, 106, and 108 begins anew. A modified circuit layout is generated in step 104, and DRC and LVS are performed on the modified circuit layout in step 106. In step 108, parasitics are again extracted from the modified circuit layout. Thus, the circuit design cycle comprising steps 102, 104, 106, and 108 as discussed above is repeated until circuit design and simulation step 102 can be performed with a high degree of confidence in the parasitic values that correspond to the circuit layout. As discussed above, the repetitive circuit design cycle significantly increases the time-to-market for integrated circuits.
Some design systems attempt to limit the repetitive circuit design cycle for integrated circuits comprising an inductor by limiting the designer""s choice of parameters corresponding to the inductor to a pre-selected number of values. For example, a design system for an integrated circuit comprising an inductor may offer a circuit designer a limited choice of fixed values for input parameters xe2x80x9ctotal widthxe2x80x9d and xe2x80x9ctotal lengthxe2x80x9d of the inductor""s layout. Since the parasitics of inductors with a limited number of fixed parameter values can be extracted, and thus determined in advance, the repetitive circuit design cycle for integrated circuits comprising those inductors, i.e. with fixed parameter values, can be reduced. However, these design systems attain a reduction in the repetitive circuit design cycle by severely limiting a circuit designer""s flexibility in designing integrated circuits comprising inductors.
Therefore, there exists a need for an integrated design system that provides a reduction in the time-to-market for integrated circuits comprising inductors. More specifically, there exists a need for an integrated design system that is able to predict the parasitics that will result from an inductor layout before the layout is generated, and thereby minimize undesirable repetition of the circuit design cycle.
The present invention is directed to method and system for predictive layout generation for inductors with reduced design cycle. The invention provides a reduction in the time-to-market for integrated circuits comprising inductors. More specifically, the invention is an integrated design system that is able to predict the parasitics that will result from an inductor layout before the layout is generated, thereby minimizing undesirable repetitions in the circuit design cycle.
In one embodiment, the invention receives a number of parameter values for an inductor, such as a spiral inductor. Examples of the parameter values are Number of Turns, Spacing, Width, Xsize, and Ysize parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the inductor are determined. For example, parasitic resistor values and parasitic capacitor values of the inductor are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the inductor.
According to the present invention, an inductor layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the inductor. As such, the parasitic values of the inductor have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the inductor for further circuit simulations.